At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. Job Title: Principal Verification Engineer (Memory) Location: Cork or Dublin Reports to: Design Engineering Director Job Overview The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) for a variety of High-Tech Markets. The Cadence IP solutions allow our Customers to tackle IP-to-SoC development in a system context, enabling them to focus on product differentiation and to reduce time to volume. This is an opportunity to join a development team designing state-of-the‑art DDR memory controllers to be used in a wide range of applications including Datacenter, Edge computing, Automotive, and AI. Cadence is a leading provider of IP solutions for the biggest names in the technology industry. The Principal Verification Engineer will be based in Cork, Dublin or Galway, as part of an experienced Controller IP Team with long established Controller development sites in Europe, US and India. Job Responsibilities Architecture of Verification Environments for complex IP such as Ethernet, CXL, Storage. Development of UVM‑SV Scoreboards for self-checking regressions. Development of Functional Coverage as part of Metric Driven Verification Environments. Development of SystemVerilog Assertions for use in Formal and Simulation Environments. Definition and Management of Verification Plans (vPlans) using Cadence vManager tools. Creation and Management of Automated Regression Environments, e.g. Jenkins. Participation in Technical Review Meetings and Checklist Reviews as part of ISO‑9001. Close Collaboration with Design Engineers to debug complex test scenarios. Job Qualifications Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline. 10-15 years’ experience in microelectronics/EDA industry. Experience of Verilog RTL Design essential. Experience of Metric Driven Verification (MDV) essential. Excellent oral and written English essential. Self-motivated with excellent planning, interpersonal, and communication skills. Additional Skills/Preferences Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis preferred. Experience of Quality processes, such as ISO‑9001 & ISO‑26262 preferred. AXI and/or CHI experience is highly desirable. Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. Travel We’re doing work that matters. Help us solve what others can’t. #J-18808-Ljbffr
A technology solutions firm in Ireland is seeking a Principal Verification Engineer to join their Controller IP Team. This role involves creating Verification Environments for complex IP, managing Verification Plans, and collaborating with Design Engineers. Candidates should have a degree in Electrical or Electronic Engineering and 10-15 years’ experience in the microelectronics/EDA industry, with strong skills in Verilog RTL Design and Metric Driven Verification. Excellent communication skills are essential. The position may be based in Cork or Dublin. #J-18808-Ljbffr
A leading technology company is seeking a Principal Verification Engineer to join their team in Cork or Dublin. The engineer will focus on developing state-of-the-art IP verification environments and work closely with design engineers. Requirements include a degree in Electrical Engineering and 10-15 years of experience in the microelectronics industry. Strong skills in Verilog RTL Design and Metric Driven Verification are essential, along with excellent communication abilities. The position involves collaboration and contribution to innovative technology solutions. #J-18808-Ljbffr
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. Job Title: Principal Verification Engineer (Memory) Location: Cork or Dublin Reports to: Design Engineering Director Job Overview The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) for a variety of High-Tech Markets. The Cadence IP solutions allow our Customers to tackle IP-to-SoC development in a system context, enabling them to focus on product differentiation and to reduce time to volume. This is an opportunity to join a development team designing state-of-the‑art DDR memory controllers to be used in a wide range of applications including Datacenter, Edge computing, Automotive, and AI. Cadence is a leading provider of IP solutions for the biggest names in the technology industry. The Principal Verification Engineer will be based in Cork, Dublin or Galway, as part of an experienced Controller IP Team with long established Controller development sites in Europe, US and India. Job Responsibilities Architecture of Verification Environments for complex IP such as Ethernet, CXL, Storage. Development of UVM‑SV Scoreboards for self-checking regressions. Development of Functional Coverage as part of Metric Driven Verification Environments. Development of SystemVerilog Assertions for use in Formal and Simulation Environments. Definition and Management of Verification Plans (vPlans) using Cadence vManager tools. Creation and Management of Automated Regression Environments, e.g. Jenkins. Participation in Technical Review Meetings and Checklist Reviews as part of ISO‑9001. Close Collaboration with Design Engineers to debug complex test scenarios. Job Qualifications Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline. 10-15 years’ experience in microelectronics/EDA industry. Experience of Verilog RTL Design essential. Experience of Metric Driven Verification (MDV) essential. Excellent oral and written English essential. Self-motivated with excellent planning, interpersonal, and communication skills. Additional Skills/Preferences Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis preferred. Experience of Quality processes, such as ISO‑9001 & ISO‑26262 preferred. AXI and/or CHI experience is highly desirable. Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. Travel We’re doing work that matters. Help us solve what others can’t. #J-18808-Ljbffr
